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RIBFDAQ uses VMIVME7807 and VMIVME7768 which are VME CPU Board. It has Tundra Universe II PCI-VME Bridge, here this linux device driver is modified by H.B. to get better performance. Main changes are the DMA-end detection, usually the DMA-end is detected by the interrupt signal but, in our case, it is detected by CPU polling. The interrupt latency (time to wake up interrupt service routine) is more than 20us (in linux case), and it is non-negligible especially for small size of DMA transfer (Usually, the size of DMA transfer in DAQ is small). Of course, with CPU polling, other processes cannot work during the DMA transfer. So this is non-standard way but much faster.


To use interrupt, it is better not to share the VME IRQ and other devices. It is possible to check by

cat /proc/interrupt

  0:    4508005          XT-PIC  timer
  1:          8          XT-PIC  i8042
  2:          0          XT-PIC  cascade
  3:     199024          XT-PIC  uhci_hcd:usb1, eth0
  7:   17878398          XT-PIC  babildrv
  8:          1          XT-PIC  rtc
  9:          0          XT-PIC  uhci_hcd:usb2
 10:          0          XT-PIC  ehci_hcd:usb3
 12:          4          XT-PIC  i8042
 15:       5336          XT-PIC  ide1
NMI:          0 
LOC:    4507439 
ERR:          0
MIS:          0

This case, the IRQ line 7 is used by babildrv only. If not, it is better to disable some devices (serial port, IRQ for VGA etc.)

in BIOS.

Mapping window

Usually, VME modules are mapped into PCI memory area. VMIVME (Tundra Universe II chip) can create upto 8 mapping windows. It is easy to use that 1 module per 1 mapping window. To use more than 8 modules, you should merge multiple modules into 1 mapping window. In this case, these modules should have closer VME addresses as far as possible. Following case is 6 modules into 1 mapping window:

Module 1 : 0x00100000
Module 2 : 0x00110000
Module 3 : 0x00120000
Module 4 : 0x00130000
Module 5 : 0x00140000
Module 6 : 0x00150000

Mapping base address = 0x00100000
Mapping window size  = 0x00060000

To access each module,

                 Base addr.  Size        AM   ID
univ_init_window(0x00100000, 0x00060000, 0x09, 1);  // Create mapping window
                Offset addr. rval ID
univ_map_read32( 0x00010000, &val, 1);  // Read data from Module 1 + 0x0000
                Offset addr. wval ID
univ_map_write32(0x00031016, &val, 1);  // Write data to Module 3 + 0x1016

Please note that, the maximum number of DMA window is 20.


DMA transfer modes of BLT+BERR and BLT+CBLT are available (if module has the capability). Some VME crates cannot work CBLT. For example, Schroff VME crate could work CBLT, but Wiener VME crate in DALI couldn't work. These are very useful for the DMA transfer with flexible length data. BLT+BERR is good for readout the large number of data from 1 module. CBLT+BERR is very nice for readout 1 event data from many modules. For CAEN V775/V787/V792 case, CBLT returns BERR every 1 event readout. E.G., to readout 10 multiple events, 10 times CBLT transactions are required.

  • The number of multiple event > The number of modules => BLT+BERR is better
  • The number of multiple event < The number of modules => CBLT+BERR is better


In RIBFDAQ network area, VMIVME can boot by downloading the linux OS image from a server. Initialize scripts are these:

ribfdaq:/home/daq/daqconfig/NAME/init/daqbootrc (for boot time only)
ribfdaq:/home/daq/daqconfig/NAME/init/daqinitrc (for initialization)

'daqbootrc' is called at boot time once. 'daqinitrc' is called at boot time and when the "INIT" button in Web Process Manager is pushed.


Aug.2 2010
The device driver for kernel 2.6.18 is available. Original interrupt handlers are deleted, All interrupts are handled by babildrv.
BERR detection during DMA transfer is available. If BERR is generated, the DMA transfer is terminated. univ_dma_segdata() copies valid data only.

Last-modified: Mon, 24 Dec 2018 21:14:28 HAST (1808d)