----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:05:30 09/24/2009 
-- Design Name: 
-- Module Name:    VLUPOIORegister - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity VLUPOIORegister is
	port (
		LED			  : out	STD_LOGIC_VECTOR (7 downto 0);
		LVDS_CLKn	: in  STD_LOGIC;
		LVDS_CLKp	: in  STD_LOGIC;
		LVDSn		  : in  STD_LOGIC_VECTOR (15 downto 0);
		LVDSp		  : in  STD_LOGIC_VECTOR (15 downto 0);
--		LVDSn		  : out STD_LOGIC_VECTOR (15 downto 0);
--		LVDSp		  : out STD_LOGIC_VECTOR (15 downto 0);
		A					: in	STD_LOGIC_VECTOR (7 downto 0);
		CLOCK			: in	STD_LOGIC;
		INIT			: in	STD_LOGIC;
		IP0				: in	STD_LOGIC;
		IP				: in	STD_LOGIC_VECTOR (3 downto 0);
		UDI				: in	STD_LOGIC_VECTOR (3 downto 0);
		UDO				: out STD_LOGIC_VECTOR (3 downto 0);
		IRQ				: out STD_LOGIC;
		OP				: out STD_LOGIC_VECTOR (3 downto 0);
		RD				: out STD_LOGIC_VECTOR (31 downto 0);
		WR				: in	STD_LOGIC_VECTOR (31 downto 0);
		RD_STRB		: in	STD_LOGIC;
		WR_STRB		: in	STD_LOGIC);
end VLUPOIORegister;

architecture Behavioral of VLUPOIORegister is

component IBUFDS
  port (
    O  : out STD_LOGIC;
    I  : in  STD_LOGIC;
    IB : in  STD_LOGIC);
end component;

component IBUFGDS
  port (
    O  : out STD_LOGIC;
    I  : in  STD_LOGIC;
    IB : in  STD_LOGIC);
end component;

component OBUFDS
  port (
    I  : in  STD_LOGIC;
	  O  : out STD_LOGIC;
		OB : out STD_LOGIC);
end component;

signal LVDSclk : std_logic;
signal LVDSio  : std_logic_vector(15 downto 0);


component DIV1M
  port ( clk : in  STD_LOGIC;
         rst : in  STD_LOGIC;
         q : out  STD_LOGIC);
end component;

component GG is
  Port ( clk   : in  STD_LOGIC;
         start : in  STD_LOGIC;
         latch : in  STD_LOGIC;
         wid   : in  STD_LOGIC_VECTOR(15 downto 0);
         q     : out STD_LOGIC);
end component;

component DLLATCH is
  Port ( clk  : in  STD_LOGIC;
				 start: in  STD_LOGIC;
         rst  : in  STD_LOGIC;
  			 veto : in  STD_LOGIC;
         dl   : in  STD_LOGIC_VECTOR(15 downto 0);
         q    : out STD_LOGIC);
end component DLLATCH;

component COIN is
  Port ( ip : in  STD_LOGIC;
         gate : in  STD_LOGIC;
         rst : in  STD_LOGIC;
         q : out  STD_LOGIC);
end component COIN;


signal nimin : std_logic;
signal gatein: std_logic;
signal clear : std_logic;
signal intr  : std_logic;
signal pwid  : std_logic_vector(15 downto 0) := x"000a";
signal intdl : std_logic_vector(15 downto 0) := x"0000";

signal lvdscoin : std_logic_vector(15 downto 0);

signal gstart    : std_logic_vector(3 downto 0) := "0000";
signal glatch    : std_logic_vector(3 downto 0) := "0000";
signal fintr     : std_logic := '1';
signal intrrst   : std_logic := '0';
signal nimcoin   : std_logic;
signal macc      : std_logic;

alias hRD : std_logic_vector(15 downto 0) is RD(31 downto 16);
alias lRD : std_logic_vector(15 downto 0) is RD(15 downto 0);
alias hWR : std_logic_vector(15 downto 0) is WR(31 downto 16);
alias lWR : std_logic_vector(15 downto 0) is WR(15 downto 0);

signal datarst : std_logic := '1';


begin

LVDSCLK_MAP : IBUFGDS
  port map (
    O  => LVDSclk,
    I  => LVDS_CLKp,
    IB => LVDS_CLKn);

LVDSIN_MAPgene : for i in 0 to 15 generate
LVDSIN_MAP : IBUFDS
  port map (
    O  => LVDSio(i),
    I  => LVDSp(i),
    IB => LVDSn(i));
end generate;

DIV1Mgate_MAP : DIV1M
  port map (
	  clk => CLOCK,
		rst => gatein,
		q => LED(0));

DIV1Mnimin_MAP : DIV1M
  port map (
	  clk => CLOCK,
		rst => nimin,
		q => LED(2));

DIV1Mclear_MAP : DIV1M
  port map (
	  clk => CLOCK,
		rst => clear,
		q => LED(4));

DIV1Mintr_MAP : DIV1M
  port map (
	  clk => CLOCK,
		rst => intr,
		q => LED(6));

RDSTRB_MAP : DIV1M
  port map (
	  clk => CLOCK,
		rst => macc,
		q => LED(1));


DDLATCH_MAP : DLLATCH
  port map (
  	clk   => CLOCK,
		start => intr,
    rst   => intrrst,
    veto  => fintr,
    dl    => intdl,
    q     => IRQ);

NIMCOIN_MAP : COIN
  port map (
		ip   => nimin,
    gate => gatein,
    rst  => datarst,
    q    => nimcoin);

LVDSCOIN_gene : for i in 0 to 15 generate
LVDSCOIN_MAP : COIN
  port map (
		ip   => LVDSio(i),
    gate => gatein,
    rst  => datarst,
    q    => lvdscoin(i));
end generate;

GGMAP_gene : for i in 0 to 3 generate
GGMAP : GG
  port map (
  	clk => CLOCK,
    start => gstart(i),
    latch => glatch(i),
    wid   => pwid,
    q     => OP(i));
end generate;


gatein <= IP0;
nimin <= IP(1);
clear <= IP(2);
intr <= IP(3);
macc <= RD_STRB or WR_STRB;

LED(3) <= '0';
LED(5) <= '0';
LED(7) <= '0';

clk_proc : process(CLOCK)
	begin
	if(CLOCK'event and CLOCK = '1') then
		if(INIT = '1') then
			intrrst <= '1';
			datarst <= '1';
			fintr <= '1';
			pwid <= x"000a";
			intdl <= x"0000";
			glatch <= "0000";
			RD <= (others => 'Z');
		elsif(RD_STRB = '1') then
			pwid <= pwid; intdl <= intdl;
			gstart <= "0000";
			glatch <= glatch;
      case A is
				when x"00" => hRD <= LVDSio;   lRD <= (others => '0');
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
				when x"02" => lRD <= lvdscoin; hRD <= (others => '0');	datarst <= '0';
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
				when x"04" => RD(16) <= nimin;   RD(31 downto 17) <= (others => '0'); RD(15 downto 0) <= (others => '0');
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
				when x"06" => RD(0) <= nimcoin;  RD(31 downto 1) <= (others => '0');
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
				when x"40" => hRD <= pwid;    lRD <= (others => '0'); -- Pulse width
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
				when x"42" => lRD <= intdl;   hRD <= (others => '0');	-- Int delay
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
				when x"90" => intrrst <= '1'; datarst <= '1';  RD <= (others => '0'); -- Clear
				when others => RD <= (others => '0');
					if(clear = '0') then
						datarst <= '0';	intrrst <= '0';
					end if;
			end case;
		elsif(WR_STRB = '1') then
			RD <= (others => 'Z');
			if(clear = '0') then
				datarst <= '0'; intrrst <= '0';
			end if;
      case A is
				when x"00" => glatch <= WR(19 downto 16); gstart <= WR(19 downto 16); -- Level out
					fintr <= fintr;	pwid <= pwid; intdl <= intdl; 
				when x"10" => glatch <= glatch and (not WR(19 downto 16)); gstart <= WR(19 downto 16);   -- Pulse out
					fintr <= fintr;	pwid <= pwid; intdl <= intdl;
				when x"40" => pwid  <= hWR;
					gstart <= "0000";	intdl <= intdl; glatch <= glatch;
				when x"42" => intdl <= lWR;
					gstart <= "0000"; pwid <= pwid; glatch <= glatch;
				when x"80" => fintr <= '1'; -- Disable interrupt
					gstart <= "0000"; pwid <= pwid; intdl <= intdl; glatch <= glatch;
				when x"a0" => fintr <= '0'; -- Enable interrupt
					gstart <= "0000"; pwid <= pwid; intdl <= intdl; glatch <= glatch;
				when others => 	gstart <= "0000";	fintr <= fintr; pwid <= pwid; intdl <= intdl; glatch <= glatch;
			end case;
		else
			datarst <= '0'; intrrst <= '0';
			pwid <= pwid; intdl <= intdl;
			RD <= (others => 'Z');
			gstart <= "0000"; glatch <= glatch;
			fintr <= fintr; 
		end if;

		if(clear = '1') then
-- Clear input
			intrrst <= '1';
			datarst <= '1';
		end if;
		
		end if;
	end process clk_proc;


end Behavioral;