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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:28:34 10/05/2009 
-- Design Name: 
-- Module Name:    RSFF - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RSFF is
    Port ( S : in  STD_LOGIC;
           R : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end RSFF;

architecture Behavioral of RSFF is
signal iQ : std_logic;

begin

--iQ  <= R nor iQb;
--iQb <= (S and not R) nor iQ;

Q  <= iQ;

	process(R, S)
		begin
		if(R = '1') then
			iQ <= '0';
		elsif(S'event and S = '1') then
			iQ <= '1';
		end if;
  end process;

end Behavioral;