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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:05:22 09/28/2009 
-- Design Name: 
-- Module Name:    GG - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GG is
    Port ( clk   : in  STD_LOGIC;
           start : in  STD_LOGIC;
           latch : in  STD_LOGIC;
           wid   : in  STD_LOGIC_VECTOR(15 downto 0);
           q     : out STD_LOGIC);
end GG;

architecture Behavioral of GG is

signal cnt : std_logic_vector(15 downto 0) := x"0000";
signal iq  : std_logic := '0';
signal fiq : std_logic := '0';

begin

q <= iq;

clk_proc : process(clk)
	begin
		if(clk'event and clk = '1') then
			if(start = '1') then
				if(iq = '0' and fiq = '0') then
					iq <= '1';
					cnt <= (others => '0');
				end if;
			else
				fiq <= '0';
			end if;

			if(start = '1' and iq = '1') then
				fiq <= '1';
			end if;

			if(latch = '0') then			
				if(wid = cnt) then
					iq <= '0';
				else
					cnt <= cnt + '1';
				end if;
			else
				if(start = '0') then
					cnt <= wid;
				end if;
			end if;
		end if;
	end process clk_proc;

end Behavioral;