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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:14:18 10/01/2009 
-- Design Name: 
-- Module Name:    DLLATCH - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DLLATCH is
    Port ( clk   : in  STD_LOGIC;
					 start : in  STD_LOGIC;
           rst   : in  STD_LOGIC;
					 veto  : in  STD_LOGIC;
           dl    : in  STD_LOGIC_VECTOR(15 downto 0);
           q     : out STD_LOGIC);
end DLLATCH;

architecture Behavioral of DLLATCH is

signal cnt : std_logic_vector(15 downto 0) := x"0000";
signal istart : std_logic := '0';

begin

  process(clk, rst, veto)
  begin
	  if(veto = '1' or rst = '1') then
		  cnt <= (others => '0');
			q <= '0';
			istart <= '0';
    elsif(clk'event and clk = '1') then
			if(start = '1') then
				istart <= '1';
			end if;

			if(istart = '1') then
				if(cnt = dl) then
					q <= '1';
				else
					cnt <= cnt + '1';
				end if;
			end if;
		end if;
	end process;

end Behavioral;