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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:16:42 09/25/2009 
-- Design Name: 
-- Module Name:    DIV1M - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DIV1M is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end DIV1M;

architecture Behavioral of DIV1M is

signal cnt : std_logic_vector(19 downto 0) := x"00000";
signal iq : std_logic := '0';

begin

q <= iq;

  process(clk, rst)
	begin
		if(rst = '1') then
			cnt <= (others => '0');
			iq <= '1';
		elsif(clk'event and clk = '1') then
			if(cnt = 999999) then
				cnt <= (others => '0');
        iq <= '0';
			else
				cnt <= cnt + '1';
			end if;
		end if;
	end process;


end Behavioral;