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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:28:46 10/05/2009 
-- Design Name: 
-- Module Name:    COIN - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity COIN is
    Port ( ip : in  STD_LOGIC;
           gate : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end COIN;

architecture Behavioral of COIN is

component RSFF is
  Port ( S : in  STD_LOGIC;
         R : in  STD_LOGIC;
         Q : out  STD_LOGIC);
end component RSFF;

signal rs1, rs1g, ipg, rs2, iq, ipgrs2 : std_logic;
signal irst : std_logic;

begin
RSFF1MAP : RSFF
	port map(
		S => gate,
		R => rst,
		Q => rs1);

RSFF2MAP : RSFF
  port map(
		S => rs1g,
		R => rst,
		Q => rs2);

RSFF3MAP : RSFF
  port map(
		S => ipgrs2,
		R => rst,
		Q => iq);

q <= iq;

rs1g <= (not gate) and rs1;
ipg  <= ip and gate;
ipgrs2  <= ipg and (not rs2);
	
end Behavioral;