----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:05:30 09/24/2009 
-- Design Name: 
-- Module Name:    CLUPOIORegister - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity CLUPOOutputRegister is
	port (
    LED			  : out	STD_LOGIC_VECTOR (7 downto 0);
    LVDS_CLKn	: in  STD_LOGIC;
    LVDS_CLKp	: in  STD_LOGIC;
--		LVDSn		  : in  STD_LOGIC_VECTOR (15 downto 0);
--		LVDSp		  : in  STD_LOGIC_VECTOR (15 downto 0);
    LVDSn		  : out STD_LOGIC_VECTOR (15 downto 0);
    LVDSp		  : out STD_LOGIC_VECTOR (15 downto 0);
    A					: in	STD_LOGIC_VECTOR (7 downto 0);
    CLOCK			: in	STD_LOGIC;
    INIT			: in	STD_LOGIC;
    IP0				: in	STD_LOGIC;
    IP				: in	STD_LOGIC_VECTOR (3 downto 0);
    UDI				: in	STD_LOGIC_VECTOR (3 downto 0);
		UDO				: out STD_LOGIC_VECTOR (3 downto 0);
		IRQ				: out STD_LOGIC;
		OP				: out STD_LOGIC_VECTOR (3 downto 0);
		RD				: out STD_LOGIC_VECTOR (31 downto 0);
		WR				: in	STD_LOGIC_VECTOR (31 downto 0);
		RD_STRB		: in	STD_LOGIC;
		WR_STRB		: in	STD_LOGIC);
end CLUPOOutputRegister;

architecture Behavioral of CLUPOOutputRegister is

component IBUFDS
  port (
    O  : out STD_LOGIC;
    I  : in  STD_LOGIC;
    IB : in  STD_LOGIC);
end component;

component IBUFGDS
  port (
    O  : out STD_LOGIC;
    I  : in  STD_LOGIC;
    IB : in  STD_LOGIC);
end component;

component OBUFDS
  port (
    I  : in  STD_LOGIC;
	  O  : out STD_LOGIC;
		OB : out STD_LOGIC);
end component;

component DIV1M
  port (
	  clk : in  STD_LOGIC;
		rst : in  STD_LOGIC;
		q   : out STD_LOGIC);
end component;

signal LVDSclk : std_logic;
signal LVDSio  : std_logic_vector(15 downto 0);

component GG is
  Port ( clk   : in  STD_LOGIC;
         start : in  STD_LOGIC;
         latch : in  STD_LOGIC;
         wid   : in  STD_LOGIC_VECTOR(15 downto 0);
         q     : out STD_LOGIC);
end component;

signal pwid  : std_logic_vector(15 downto 0) := x"000a";

signal gstart    : std_logic_vector(3 downto 0) := "0000";
signal glatch    : std_logic_vector(3 downto 0) := "0000";
signal lgstart    : std_logic_vector(15 downto 0) := x"0000";
signal lglatch    : std_logic_vector(15 downto 0) := x"0000";

signal macc      : std_logic := '0';

alias hRD : std_logic_vector(15 downto 0) is RD(31 downto 16);
alias lRD : std_logic_vector(15 downto 0) is RD(15 downto 0);
alias hWR : std_logic_vector(15 downto 0) is WR(31 downto 16);
alias lWR : std_logic_vector(15 downto 0) is WR(15 downto 0);

begin

LVDSCLK_MAP : IBUFGDS
  port map (
    O  => LVDSclk,
    I  => LVDS_CLKp,
    IB => LVDS_CLKn);

LVDSOUT_MAPgene : for i in 0 to 15 generate
LVDSOUT_MAP : OBUFDS
  port map (
    I  => LVDSio(i),
    O  => LVDSp(i),
    OB => LVDSn(i));
end generate;

RDSTRB_MAP : DIV1M
  port map (
	  clk => CLOCK,
		rst => macc,
		q => LED(1));


GGMAP_gene : for i in 0 to 3 generate
GGMAP : GG
  port map (
  	clk => CLOCK,
    start => gstart(i),
    latch => glatch(i),
    wid   => pwid,
    q     => OP(i));
end generate;

LGGMAP_gene : for i in 0 to 15 generate
LGGMAP : GG
  port map (
  	clk => CLOCK,
    start => lgstart(i),
    latch => lglatch(i),
    wid   => pwid,
    q     => LVDSio(i));
end generate;

macc <= RD_STRB or WR_STRB;
IRQ <= '0';

LED(3) <= '0';
LED(5) <= '0';
LED(7) <= '0';


clk_proc : process(CLOCK, INIT)
	begin
		if(INIT = '1') then
			pwid <= x"000a";
			glatch <= "0000";
			lglatch <= x"0000";
			gstart <= "0000";
			lgstart <= x"0000";
			RD <= (others => '0');
		elsif(CLOCK'event and CLOCK = '1')then
	    if(RD_STRB = '1') then
				pwid <= pwid;
				glatch <= glatch;
				lglatch <= lglatch;
				gstart <= "0000";
				lgstart <= x"0000";
        case A is
					when x"40" => lRD <= pwid;  hRD <= (others => '0'); -- Pulse width
					when others => RD <= (others => '0');
				end case;
      elsif(WR_STRB = '1') then
				RD <= (others => '0');
        case A is
					when x"00" => glatch <= WR(3 downto 0); gstart <= WR(3 downto 0); -- Level out
						pwid <= pwid;  lglatch <= lglatch;  lgstart <= x"0000";
					when x"10" => glatch <= glatch and (not WR(3 downto 0)); gstart <= WR(3 downto 0);   -- Pulse out
						pwid <= pwid;  lglatch <= lglatch;  lgstart <= x"0000";
					when x"20" => lglatch <= lWR; lgstart <= lWR; -- Level out
						pwid <= pwid;  glatch <= glatch;  gstart <= "0000";
					when x"30" => lglatch <= lglatch and (not lWR); lgstart <= lWR;  -- Pulse out
						pwid <= pwid;  glatch <= glatch;  gstart <= "0000";
					when x"40" => pwid  <= lWR;
						glatch <= glatch;  gstart <= "0000"; lglatch <= lglatch;  lgstart <= x"0000";
					when others => pwid <= pwid;  glatch <= glatch;  gstart <= "0000"; lglatch <= lglatch;  lgstart <= x"0000";
				end case;
      else
				pwid <= pwid;  glatch <= glatch; lglatch <= lglatch;
				RD <= (others => '0');
				gstart <= "0000";
				lgstart <= x"0000";
				LED(0) <= glatch(0);
				LED(2) <= glatch(1);
				LED(4) <= glatch(2);
				LED(6) <= glatch(3);
			end if;
		end if;
	end process clk_proc;


end Behavioral;